Willow Cove

CPU microarchitecture by Intel
  • Intel
CacheL1 cache80 KB per core:
(32 KB instructions + 48 KB data)Architecture and classificationTechnology nodeIntel 10 nm SuperFin (10SF)Instruction setx86-64Extensions
  • AES-NI, CLMUL, RDRAND, SHA, TXT, MMX, SSE, SSE2, SSE3, SSSE3, SSE4, SSE4.1, SSE4.2, AVX, AVX2, AVX-512, FMA3, VT-x, VT-d
Products, models, variantsProduct code name(s)HistoryPredecessor(s)Sunny CoveSuccessor(s)Golden Cove

Willow Cove is a codename for a CPU microarchitecture developed by Intel and released in September 2020. Willow Cove is the successor to the Sunny Cove microarchitecture, and is fabricated using Intel's enhanced 10 nm process node called 10 nm SuperFin (10SF).[1] The microarchitecture powers 11th-generation Intel Core mobile processors (codenamed "Tiger Lake").[1][2]

The Willow Cove microarchitecture was succeeded by Golden Cove.[3]

Features

Intel first described Tiger Lake and Willow Cove during their Architecture Day in 2020.[4] Willow Cove is almost identical to the previous microarchitecture but introduces new security features, a redesigned cache subsystem, and higher clock speeds.[4] Intel claims that these changes, in addition to the new 10SF process node, give an additional 10–20% performance increase from Sunny Cove.[1]

Improvements

  • Larger L2 caches (1.25 MB per core from 512 KB per core)
  • Larger L3 caches (3 MB per core from 2 MB per core)
  • A new AVX-512 instruction: Vector Pair Intersection to a Pair of Mask Registers, VP2INTERSECT[5][6]
  • Control Flow Enforcement Technology to prevent return-oriented programming and jump-oriented programming exploitation techniques[7]
  • Full memory (RAM) encryption[8]
  • Indirect branch tracking and shadow stack
  • Intel Key Locker[9][10]
  • AVX/AVX2 instructions support for Pentium Gold and Celeron processors has been unlocked[6]

Products

Willow Cove powers Intel's 11th-generation Intel Core mobile processors (codenamed Tiger Lake). Tiger Lake-U processors were released on September 2, 2020,[11] while Tiger Lake-H35 were released on January 11, 2021.[12] Tiger Lake-H processors were launched on May 11, 2021.[13][14]

References

  1. ^ a b c Cutress, Dr Ian. "Intel's 11th Gen Core Tiger Lake SoC Detailed: SuperFin, Willow Cove and Xe-LP". www.anandtech.com. Retrieved 2021-04-06.
  2. ^ "Intel teases its Ice Lake & Tiger Lake family, 10nm for 2018 and 2019". TweakTown. 2016-01-20. Retrieved 2021-02-15.
  3. ^ Cutress, Dr Ian. "Intel Alder Lake: Confirmed x86 Hybrid with Golden Cove and Gracemont for 2021". www.anandtech.com. Retrieved 2021-02-15.
  4. ^ a b "Intel goes over Tiger Lake and Willow Cove at Architecture Day". Windows Central. 2020-08-13. Retrieved 2021-04-06.
  5. ^ "Compiler Support Getting Wired Up For AVX-512 VP2INTERSECT - Phoronix". www.phoronix.com. Retrieved 2020-01-14.
  6. ^ a b October 2020, Anton Shilov 16 (16 October 2020). "Intel's Latest Celeron and Pentium CPUs Finally Get AVX2, AVX-512 Support". Tom's Hardware. Retrieved 2020-10-19.{{cite web}}: CS1 maint: numeric names: authors list (link)
  7. ^ "A Technical Look at Intel's Control-flow Enforcement Technology". Intel. Retrieved 2020-09-02.
  8. ^ "Intel Releases New Technology Specification for Memory Encryption". Intel. Retrieved 2020-09-02.
  9. ^ "Intel Key Locker Specification" (PDF). Retrieved 2023-10-11.
  10. ^ "Intel Key Locker Support Added to LLVM - Confirms Presence with Tiger Lake - Phoronix".
  11. ^ "2019 Intel Investor Meeting: The Transformation of the PC Sector" (PDF). 2019 Intel Investor Meeting. May 8, 2019. p. 11. Retrieved 2019-05-19.
  12. ^ Cutress, Dr Ian. "Intel's New H35 Series: Quad Core Tiger Lake now at 35 W for 5.0 GHz". www.anandtech.com. Retrieved 2021-01-12.
  13. ^ Cutress, Dr Ian. "Intel Launches 11th Generation Core Tiger Lake-H: Eight Core 10nm Mobile Processors". www.anandtech.com. Retrieved 2021-05-21.
  14. ^ Cutress, Dr Ian. "Intel's 8-Core Mobile Tiger Lake-H, at 45 W, to Ship in Q1". www.anandtech.com. Retrieved 2021-01-12.
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Intel CPU core roadmaps from P6 to Lunar Lake
Atom (ULV) Feature size Pentium/Core
Microarch. Step Microarch. Step
600 nm P6 Pentium Pro
(133 MHz)
500 nm Pentium Pro
(150 MHz)
350 nm Pentium Pro
(166–200 MHz)
Klamath
250 nm Deschutes
Katmai NetBurst
180 nm Coppermine Willamette
130 nm Tualatin Northwood
Pentium M Banias NetBurst(HT) NetBurst(×2)
90 nm Dothan Prescott Prescott‑2M Smithfield
Tejas Cedarmill (Tejas)
65 nm Yonah Nehalem (NetBurst) Cedar Mill Presler
Core Merom 4 cores on mainstream desktop, DDR3 introduced
Bonnell Bonnell 45 nm Penryn
Nehalem Nehalem HT reintroduced, integrated MC, PCH
L3-cache introduced, 256KB L2-cache/core
Saltwell 32 nm Westmere Introduced GPU on same package and AES-NI
Sandy Bridge Sandy Bridge On-die ring bus, no more non-UEFI motherboards
Silvermont Silvermont 22 nm Ivy Bridge
Haswell Haswell Fully integrated voltage regulator
Airmont 14 nm Broadwell
Skylake Skylake DDR4 introduced on mainstream desktop
Goldmont Goldmont Kaby Lake
Coffee Lake 6 cores on mainstream desktop
Amber Lake Mobile-only
Goldmont Plus Goldmont Plus Whiskey Lake Mobile-only
Coffee Lake Refresh 8 cores on mainstream desktop
Comet Lake 10 cores on mainstream desktop
Sunny Cove Cypress Cove (Rocket Lake) Backported Sunny Cove microarchitecture for 14nm
Tremont Tremont 10 nm Skylake Palm Cove (Cannon Lake) Mobile-only
Sunny Cove Sunny Cove (Ice Lake) 512 KB L2-cache/core
Willow Cove (Tiger Lake) Xe graphics engine
Gracemont Gracemont Intel 7 Golden Cove Golden Cove (Alder Lake) Hybrid, DDR5, PCIe 5.0
Raptor Cove (Raptor Lake)
Crestmont Crestmont Intel 4 Redwood Cove Meteor Lake Mobile-only
NPU, chiplet architecture
Skymont Skymont Intel 20A Lion Cove Arrow Lake
TBA TBA Intel 18A
or 20A
TBA Lunar Lake
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